Mike's Notes
Pipi doesn't use vectors, which means no real need for GPUs. Pipi 9 is designed to run on CPUs. I wonder if part of it could also run on Cerebras Wafer-Scale Engine-3 (WSE-3) and maybe occasionally leased TPUs.
Here are some initial working notes copied from the Cerebras SDK, along with a few questions.
Later, there will be initial experimental code written that Pipi could run via Python on 900,000 AI cores on a single wafer.
- Wafers are the size of dinner plates and are more power-efficient than GPUs because they store memory and processing together at each core.
- GPUs use matrix multiplication, which is expensive because it moves vast amounts of data between different chips.
This is a long shot, would be very expensive to implement, and will need a lot of discovery and learning😎. But using GPUs at scale is also expensive.
All efforts are to reduce costs while improving function.
Resources
- https://en.wikipedia.org/wiki/Cerebras_Systems
- http://sdk.cerebras.ai/
- https://github.com/Cerebras/sdk-examples/tree/rel-sdk-2.10.0
- https://github.com/Cerebras/sdk-examples/tree/master
- https://www.cerebras.ai/blog
- https://discourse.cerebras.net/
- https://training-docs.cerebras.ai/rel-2.5.0/getting-started/overview
- https://ai-sdk.dev/providers/ai-sdk-providers/cerebras
- https://inference-docs.cerebras.ai/
- https://www.blog.ajabbi.com/2025/05/a-three-data-centre-model-for-pipi.html
References
- Reference
Repository
- Home > Ajabbi Research > Library >
- Home > Handbook >
Last Updated
22/08/2026
Running Pipi on Cerebras using SDK
Mike is the inventor and architect of Pipi and the founder of Ajabbi.
Big picture
- Pipi runs very well on CPUs. 200 autonomous agents can run on a 16GB utility server. Without using vectors.
- Running genetic algorithms in a fitness landscape would be better done on a Cerebras Wafer-Scale Engine. I need to test that assumption with some simple experiments.
- Got CSL and Python code ready to test.
- Can test on a local sandbox and then run further tests on a VM in the cloud using cheap spot compute.
- Start with small arrays and scale up, trying different fitness algorithms.
- Pipi could easily automatically run this deploy to GCP, run, get result, destroy cloud deployment.
- Later, run directly on Cerebras (will require research grade, given using SDK to directly configure wafer cores).
- Talk to Andrew at SemiAnalysis.
From Cerebras SDK
"
Cerebras SDK: A Conceptual View
Learn how the Wafer-Scale Engine architecture works, how processing elements communicate, and how the host and device interact.
The Cerebras Wafer-Scale Engine (WSE) is a wafer-parallel compute accelerator, containing hundreds of thousands of independent processing elements (PEs). The PEs are interconnected by communication links into a two-dimensional rectangular mesh on one single silicon wafer. Each PE has its own memory (used by it and no other) and its own program counter. It has its own executable code in its memory. 32-bit messages, called wavelets, can be sent to or received by neighboring PEs in a single clock cycle.
The PE also has dataflow control characteristics. An instruction can terminate the currently running thread (called a task), at which time, hardware selects a new task from among the set of tasks that constitute the PE’s code. It selects a runnable task, one that has been activated (and unblocked; we will describe this in more detail later). Incoming wavelets travel along a virtual channel, called a color. All colors transfer data on a single physical channel. The congestion of one color does not block the traffic of another color. For each color used for incoming wavelets, there may be a task that is activated by its arrival.
The Cerebras System (CS) is a self-contained rack-mounted system containing packaging, power supply, cooling and I/O for a single WSE. The CS communicates via parallel 100 Gigabit ethernet connections to a host CPU cluster. Throughout this documentation, the CS is referred to as the “device,” the host CPU cluster as the “host,” and the ethernet connections connecting the two as “host I/O”. The SDK provides mechanisms for using host I/O to move data between host and device or launch functions on the device.
The below figure gives a visual representation of the mesh of PEs that make up the WSE, and its connections to the outside world. Data is streamed onto the device via host I/O, and enters the WSE through a series of links along its edges. The programming model of the SDK abstracts away the details of these links, and allows the programmer to copy data from the host to arbitrary PEs on the device.
A Processing Element (PE)
A PE contains three key elements:
- A processor. Also referred as a compute engine (CE).
- A router. The router of a PE is directly connected via bidirectional links to its own CE and to the routers of the four nearest neighboring PEs in the mesh. The link to its own CE is called the RAMP, and the links to the four neighboring PEs are referred to by their cardinal directions. The router is the only communication device the PEs use to send and receive data.
- The local PE memory. All of the PE’s data and code are stored within this memory. Neither the CE nor the local memory of a PE is directly accessible by other PEs.
The Programming Model
To develop code for the WSE, you write device code in the Cerebras Software Language (CSL), and host code in Python. You then compile the device code, and run your program on either the Cerebras fabric simulator, or the actual network-attached device. The host code is responsible for copying data to and from the device, and launching discrete programs referred to as kernels.
... "
Cost guesstimates
- WSE-3
- Buy
- Capex $20M USD from Cerebras
- Power usage of 25KW works out at $6,500 NZD/month
- Rent
- Who?
- Where?
- How Much?
